Layout Designer and Physical Design Engineer - NOC

[anilm90]

Hi ,

Which NOC would be most suitable for below Job Description :

• Responsible for Design and development of standard cell layouts.
• Designed layouts for standard cell architecture in 250nm, 180nm, 90nm, 65nm and 28nm .
• Designed layouts for basic combinational cells like NAND, ADDERS, MUX and Sequential cells.
• Used Cadence Virtuoso for layout and schematic drawing.
• Used Cadence Encounter for the Place and Route of the standard cell validation.

Note : This is VLSI Semiconductor domain.

2133/2147/2253 - Are the options I see.

Thanks
anilm